(China (Mainland))
Product Summary
The H5PS5162FFR-Y5C is a 512Mb DDR2 sdram.
Parametrics
H5PS5162FFR-Y5C absolute maximum ratings: (1)VDD Voltage on VDD pin relative to Vss: - 1.0 V ~ 2.3 V ; (2)VDDQ Voltage on VDDQ pin relative to Vss: - 0.5 V ~ 2.3 V; (3)VDDL Voltage on VDDL pin relative to Vss: - 0.5 V ~ 2.3 V; (4)VIN, VOUT Voltage on any pin relative to Vss: - 0.5 V ~ 2.3 V; (5)TSTG Storage Temperature: -55 to +100℃; (6)II Input leakage current; any input 0V VIN VDD; all other balls not under test = 0V): -2 uA ~ 2 uA ; (7)IOZ Output leakage current; 0V VOUT VDDQ; DQ and ODT disabled: -5 uA ~ 5 uA.
Features
H5PS5162FFR-Y5C features: (1)VDD ,VDDQ =1.8 +/- 0.1V; (2)All inputs and outputs are compatible with SSTL_18 interface; (3)Fully differential clock inputs (CK, /CK) operation; (4)Double data rate interface; (5)Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS); (6)Differential Data Strobe (DQS, DQS); (7)Data outputs on DQS, DQS edges when read (edged DQ); (8)Data inputs on DQS centers when write(centered DQ); (9)On chip DLL align DQ, DQS and DQS transition with CK transition; (10)DM mask write data-in at the both rising and falling edges of the data strobe; (11)All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock; (12)Programmable CAS latency 3, 4, 5 and 6 supported; (13)Programmable additive latency 0, 1, 2, 3, 4 and 5 supported; (14)Programmable burst length 4 / 8 with both nibble sequential and interleave mode; (15)Internal four bank operations with single pulsed RAS; (16)Auto refresh and self refresh supported; (17)tRAS lockout supported; (18)8K refresh cycles /64ms; (19)JEDEC standard 84ball FBGA(x16) : 8mm x 13mm; (20)Full strength driver option controlled by EMRS; (21)On Die Termination supported; (22)Off Chip Driver Impedance Adjustment supported; (23)Self-Refresh High Temperature Entry; (24)Partial Array Self Refresh support.
Diagrams
