HD6437021SC02TE

SuperHTM RISC engine, 7.0 V, TQFP

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Price:: US $11.00~11.50 / piece [Get Latest Price]

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	US $11.00~11.50

PartNumber:: HD6437021SC02TE

Brand:: Hitachi Ltd - Hitachi | Pack: TQFP | D/C: 01+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Total Price:: US $0

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Products Upload time: 2012-09-18

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Part Number:HD6437021SC02TE
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Product Summary

The HD6437021SC02TE is a SuperHTM RISC engine in which a Hitachi-original CPU and the peripheral functions required for system configuration are integrated onto a single chip. The HD6437021SC02TE has a RISC-type instruction set. Most instructions can be executed in one clock cycle, which strikingly improves instruction execution speed. In addition, the HD6437021SC02TE has a 32-bit internal architecture for enhanced data-processing ability. As a result, the HD6437021SC02TE enables high-performance systems to be constructed with advanced functionality at low cost, even in applications such as realtime control that require very high speeds, an impossibility with conventional microcomputers. The SH microcomputer includes peripheral functions such as large-capacity ROM, RAM, a direct memory access controller (DMAC), timers, a serial communication interface (SCI), an interrupt controller (INTC), and I/O ports. External memory access support functions enable direct connection to SRAM and DRAM. The HD6437021SC02TE features can drastically reduce system cost.

Parametrics

HD6437021SC02TE absolute maximum ratings: (1)Power supply voltage VCC: －0.3 to +7.0 V; (2)Program voltage VPP: －0.3 to +13.5 V; (3)Input voltage Vin: －0.3 to VCC + 0.3 V; (4)Operating temperature Topr: －20 to +75* °C; (5)Storage temperature Tstg: －55 to +125 °C.

Features

HD6437021SC02TE features: (1) CPU Original Hitachi architecture; (2) CPU 32-bit internal data paths; (3) CPU General-register machine: Sixteen 32-bit general registers, Three 32-bit control registers, Four 32-bit system registers; (4) CPU Five-stage pipeline; (5) CPU Instruction execution time: one instruction/cycle (50 ns/instruction at 20-MHz operation).