HY5PS121621CFP-25

Product Summary

The HY5PS121621CFP-25 is a 512Mb DDR2 SDRAM. All inputs and outputs of it are compatible with SSTL_18 interface.

Parametrics

HY5PS121621CFP-25 absoulte maximum ratings: (1)Voltage on VDD pin relative to Vss:-1.0V to 2.3V; (2)Voltage on VDDQ pin relative to Vss:-0.5V to 2.3V; (3)Voltage on VDDL pin relative to Vss:-0.5V to 2.3V; (4)Voltage on any pin relative to Vss:-0.5V to 2.3V; (5)Storage Temperature:-55℃ to +100℃; (6)Input leakage current; any input 0V VIN VDD; all other balls not under test = 0V:-2uA to 2uA; (7)Output leakage current; 0V VOUT VDDQ; DQ and ODT disabled:-5uA to 5uA.

Features

HY5PS121621CFP-25 features: (1)VDD ,VDDQ =1.8 +/- 0.1V; (2)All inputs and outputs are compatible with SSTL_18 interface; (3)Fully differential clock inputs (CK, /CK) operation; (4)Double data rate interface; (5)Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS); (6)Differential Data Strobe (DQS, DQS); (7)Data outputs on DQS, DQS edges when read (edged DQ); (8)Data inputs on DQS centers when write(centered DQ); (9)On chip DLL align DQ, DQS and DQS transition with CK transition; (10)DM mask write data-in at the both rising and falling edges of the data strobe; (11)All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock; (12)Programmable CAS latency 3, 4, 5 and 6 supported; (13)Programmable additive latency 0, 1, 2, 3, 4 and 5 supported; (14)Programmable burst length 4 / 8 with both nibble sequential and interleave mode; (15)Internal four bank operations with single pulsed RAS; (16)Auto refresh and self refresh supported; (17)tRAS lockout supported; (18)8K refresh cycles /64ms; (19)JEDEC standard 60ball FBGA(x4/x8) & 84ball FBGA(x16); (20)Full strength driver option controlled by EMRS; (21)On Die Termination supported; (22)Off Chip Driver Impedance Adjustment supported; (23)Read Data Strobe supported (x8 only); (24)Partial Array Self Refresh

Diagrams