HYB18T512160B2F-3S

512-Mbit Double-Data-Rate-Two SDRAM, PG-TFBGA, 1.8 V ± 0.1

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Price:: US $1.45~1.60 / piece [Get Latest Price]

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PartNumber:: HYB18T512160B2F-3S

Brand:: Qimonda AG - Qimonda | Pack: BGA | D/C: 09+

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Products Upload time: 2012-05-10

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Product Summary

The HYB18T512160B2F-3S is a 512-Mbit Double-Data-Rate-Two SDRAM. It contains 536,870,912 bits and internally configured as a quad-bank DRAM. The HYB18T512160B2F-3S is organized as either 32 Mbit × 4 I/O ×4 banks, 16 Mbit × 8 I/O × 4 banks or 8 Mbit × 16 I/O × 4 banks chip. The HYB18T512160B2F-3S achieves high speed transfer rates starting at 400 Mb/sec/pin for general applications. It is available in PG-TFBGA package.

Parametrics

HYB18T512160B2F-3S absolute maximum ratings: (1)VDD Voltage on VDD pin relative to VSS: –1.0 to +2.3 V; (2)VDDQ Voltage on VDDQ pin relative to VSS: –0.5 to +2.3 V; (3)VDDL Voltage on VDDL pin relative to VSS: –0.5 to +2.3 V; (4)VIN, VOUT Voltage on any pin relative to VSS: –0.5 to +2.3 V; (5)TSTG Storage Temperature: –55 to +100 ℃.

Features

HYB18T512160B2F-3S features: (1)1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O; (2)DRAM organizations with 4, 8 and 16 data in/outputs; (3)Double Data Rate architecture: two data transfers per clock cycle four internal banks for concurrent operation; (4)Programmable CAS Latency: 3, 4, 5 and 6; (5)Programmable Burst Length: 4 and 8; (6)Differential clock inputs (CK and CK); (7)Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read data and center-aligned with write data; (8)DLL aligns DQ and DQS transitions with clock; (9)DQS can be disabled for single-ended data strobe operation; (10)Commands entered on each positive clock edge, data and data mask are referenced to both edges of DQS; (11)Data masks (DM) for write data; (12)Posted CAS by programmable additive latency for better command and data bus efficiency.