Product Summary

The HYB25L512160AC-7.5 is a 512MBit Mobile-RAM. It consists of two 256MBit high-speed CMOS, dynamic random-access memories each of them containing 268,435,456 bits. Each chip is internally configured as a quad-bank DRAM. The HYB25L512160AC-7.5 achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to the system clock. The HYB25L512160AC-7.5 is especially designed for mobile applications: it adds many features to save power, like low operating voltages. Additionally, current consumption in self refresh mode can further be reduced by using the programmable Partial Array Self Refresh (PASR) and Temperature Compensated Self Refresh (TCSR).

Parametrics

HYB25L512160AC-7.5 absolute maximum ratings: (1)Power Supply Voltage VDD: -1.0 to 4.6 V; (2)Power Supply Voltage for Output Buffer VDDQ: -1.0 to 4.6 V; (3)Input Voltage VIN: -1.0 to VDDQ + 0.5 V; (4)Output Voltage VOUT: -1.0 to VDDQ + 0.5 V; (5)Operation Case Temperature Commercial TC: 0 to +70 ℃, Extended TC: -25 to +85 ℃; (6)Storage Temperature TSTG: -55 to +150 ℃; (7)Power Dissipation PD: 0.7 W; (8)Short Circuit Output Current IOUT: 50 mA.

Features

HYB25L512160AC-7.5 features: (1)2 × 4 banks × 4 Mbit × 16 organisation ( Two 256MBit chips stacked in multi-chip package); (2)Fully synchronous to positive clock edge; (3)Four internal banks for concurrent operation; (4)Programmable CAS latency: 2, 3; (5)Programmable burst length: 1, 2, 4, 8 or full page; (6)Programmable wrap sequence: sequential or interleaved; (7)Auto refresh and self refresh modes; (8)8192 refresh cycles / 64ms; (9)Auto precharge; (10)Operating temperature rangeCommerical (0℃ to +70℃), Extended (-25℃ to +85℃); (11)54-ball FBGA package (12.0 mm × 8.0 mm × 1.4 mm).

Diagrams

HYB25L512160AC-7.5 block diagram

HYB25D128
HYB25D128

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HYB25D128160AL
HYB25D128160AL

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HYB25D128160AT
HYB25D128160AT

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HYB25D128160CE-5
HYB25D128160CE-5

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HYB25D128160CE-6
HYB25D128160CE-6

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HYB25D128160CT-6
HYB25D128160CT-6

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