SMJ27C256-20JM

Product Summary

The SMJ27C256-20JM is a set of 262,144 bit, ultravioletlight erasable, electrically programmable read-only memories. These devices are fabricated using power-saving CMOS technology for high speed and simple interface with MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 54 TTL circuits without the use of external pullup resistors. Each output can drive one Series 54 TTL circuit without external resistors. The data outputs are 3-state for connecting multiple devices to a common bus. The SMJ27C256-20JM is pin-compatible with 28-pin 256K ROMs and EPROMs. It is offered in a 600mil dual-in-line ceramic pagackage (J suffix) rated for operation from -55℃ to 125℃. Because this EPROM operates from a single 5V supply (in the read mode), it is ideal for use in microprocessor-based systems. One other supply (13V) is needed for programming. All programming signals are TTL level. This device is programmable by the SNAP! Pulse programming algorithm.The SNAP! Pulse programming algorithm uses a VPP of 13V and a VCC of 6.5V for a nominal programming time of four seconds. For programming outside the system, existing EPROM programmers can be used. Locations can be programmed singly, in blocks, or at random.

Parametrics

Absolute maximum ratings: (1)Supply Voltage Range, VCC: -0.6V to +7.0V; (2)Supply Voltage Range, Vpp: -0.6V to +14.0V; (3)Input Voltage Range, All inputs except A9: -0.6V to +6.5V; (4)Output Voltage Range: -0.6V to VCC+1V; (5)Minimum Operating Free-air Temperature, TA: -55℃; (6)Maximum Operating Case Temperature, TC: 125℃; (7)Storage Temperature Range, Tstg: -65℃ to 150℃.

Features

Features: (1)Organized 32,768 x 8; (2)Single +5V ±10% power supply; (3)Pin-compatible with existing 256K ROM and EPROM; (4)All inputs/outputs fully TTL compatible; (5)Power-saving CMOS technology; (6)Very high-speed SNAP! Pulse Programming; (7)3-state output buffers; (8)400-mV DC assured noise immunity with standarad TTL loads; (9)Latchup immunity of 250 mA on all input and output pins; (10)Low power dissipation (CMOS Input Levels); (11)PActive - 165mW Worst Case; (12)PStandby - 1.7mW Worst Case (CMOS-input levels).

Diagrams